Clock multiplier
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United States of America Patent
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Jun 8, 2021
Grant Date -
N/A
app pub date -
Sep 3, 2020
filing date -
Dec 25, 2019
priority date (Note) -
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Abstract
A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.
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