High bandwidth register file circuit with high port counts for reduced bitline delay
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United States of America Patent
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Jun 8, 2021
Grant Date -
Nov 12, 2020
app pub date -
May 8, 2019
filing date -
May 8, 2019
priority date (Note) -
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Abstract
A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.
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