Deglitching circuit and method in class-D amplifier
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 30, 2021
Grant Date -
N/A
app pub date -
Mar 15, 2019
filing date -
Mar 15, 2019
priority date (Note) -
In Force
status (Latency Note)
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Abstract
In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
STMICROELECTRONICS (SHENZHEN) R&D CO LTD | SHENZHEN NANSHAN 518057 |
International Classification(s)

- 2019 Application Filing Year
- H03K Class
- 2785 Applications Filed
- 2122 Patents Issued To-Date
- 76.20 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Du, Ru Feng | Shenzhen, CN | 13 | 80 |
# of filed Patents : 13 Total Citations : 80 | |||
Liu, Qi Yu | Shenzhen, CN | 11 | 80 |
# of filed Patents : 11 Total Citations : 80 |
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- 0 Citation Count
- H03K Class
- 0 % this patent is cited more than
- 4 Age
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