Techniques in phase-lock loop configuration in a computing device
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United States of America Patent
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Mar 23, 2021
Grant Date -
Feb 4, 2021
app pub date -
Jul 31, 2019
filing date -
Jul 31, 2019
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Abstract
Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.
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