Processor support for hardware transactional memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 23, 2021
Grant Date -
May 3, 2018
app pub date -
Dec 18, 2017
filing date -
Jun 11, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully