Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same
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United States of America Patent
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Mar 16, 2021
Grant Date -
Sep 5, 2019
app pub date -
Apr 29, 2019
filing date -
Mar 12, 2012
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Abstract
A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.
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