Implementation of execution compression of instructions in slice target register file mapper
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 16, 2021
Grant Date -
N/A
app pub date -
Dec 20, 2018
filing date -
Dec 20, 2018
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computer system includes a dispatch routing network to dispatch a plurality of instructions, and a processor in signal communication with the dispatch routing network. The processor determines a move instruction from the plurality of instructions to move data produced by an older second instruction, and copies a splice target file (STF) tag from a source register of the move instruction to a destination register of the move instruction without physically copying data in a slice target register and without assigning a new STF tag destination to the move instruction.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully