Interposer, Test Access Port, First and Second Through Silicon Vias
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United States of America Patent
Stats
-
Feb 23, 2021
Grant Date -
May 14, 2020
app pub date -
Jan 20, 2020
filing date -
Jun 20, 2011
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
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International Classification(s)
- 2020 Application Filing Year
- B05C Class
- 449 Applications Filed
- 308 Patents Issued To-Date
- 68.60 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- B05C Class
- 0 % this patent is cited more than
- 4 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Aug 23, 2028 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Aug 23, 2032 |
