Integrated circuit clock management during low power operations
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United States of America Patent
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Jan 26, 2021
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N/A
app pub date -
Oct 18, 2019
filing date -
Oct 18, 2019
priority date (Note) -
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Abstract
An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.
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