Divider control and reset for phase-locked loops
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United States of America Patent
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Dec 22, 2020
Grant Date -
Nov 5, 2020
app pub date -
May 2, 2019
filing date -
May 2, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
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