Method for forming semiconductor device having a multi-thickness gate trench dielectric layer
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United States of America Patent
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Nov 24, 2020
Grant Date -
Oct 10, 2019
app pub date -
Jun 18, 2019
filing date -
Jul 31, 2017
priority date (Note) -
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Abstract
A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
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