Placement of vectorized latches in hierarchical integrated circuit development
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United States of America Patent
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Nov 10, 2020
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N/A
app pub date -
Jul 23, 2019
filing date -
Jul 23, 2019
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Abstract
Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.
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