Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 13, 2020
Grant Date -
Aug 29, 2019
app pub date -
Nov 7, 2017
filing date -
Dec 16, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.
First Claim
all claims..Other Claims data not available
Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
INTEL CORPORATION | 2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054 |
International Classification(s)

- 2017 Application Filing Year
- H03L Class
- 681 Applications Filed
- 583 Patents Issued To-Date
- 85.61 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Mayer, Thomas | Linz, AT | 167 | 3264 |
# of filed Patents : 167 Total Citations : 3264 | |||
Wicpalek, Christian | Puchenau, AT | 19 | 113 |
# of filed Patents : 19 Total Citations : 113 |
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Patent Citation Ranking
- 0 Citation Count
- H03L Class
- 0 % this patent is cited more than
- 5 Age
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