Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal

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United States of America Patent

PATENT NO 10804908
APP PUB NO 20190268004A1
SERIAL NO

16348184

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Abstract

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Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

International Classification(s)

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  • 2017 Application Filing Year
  • H03L Class
  • 681 Applications Filed
  • 583 Patents Issued To-Date
  • 85.61 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2017201820192020202120220255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mayer, Thomas Linz, AT 167 3264
Wicpalek, Christian Puchenau, AT 19 113

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Patent Citation Ranking

  • 0 Citation Count
  • H03L Class
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  • 5 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges25748093101 - 1011 - 2021 - 3031 - 400255075100125150175200225250275300325350375400425450475500525

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