Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal
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United States of America Patent
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Oct 13, 2020
Grant Date -
Aug 29, 2019
app pub date -
Nov 7, 2017
filing date -
Dec 16, 2016
priority date (Note) -
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Abstract
Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.
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