Fault detecting and fault tolerant multi-threaded processors
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United States of America Patent
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Sep 22, 2020
Grant Date -
Mar 7, 2019
app pub date -
Aug 10, 2018
filing date -
Aug 10, 2017
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Abstract
Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.
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