Memory array with reduced circuitry
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United States of America Patent
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Sep 1, 2020
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app pub date -
Dec 13, 2018
filing date -
Dec 13, 2018
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Abstract
A memory array is described herein that includes a static random-access memory (SRAM) array to store data. The memory array also includes a bit circuit to retrieve the data from the SRAM array, the bit circuit to be operated with a clock signal that oscillates between a low state and an intermediate state, wherein the intermediate state is between the low state and a high state. Furthermore, the memory array includes a sense amplifier to amplify an output signal from the bit circuit indicating a value of the stored data, wherein the sense amplifier does not include a cross coupled positive field-effect transistor.
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