Non-volatile split gate memory cells with integrated high K metal control gates and method of making same
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United States of America Patent
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Jul 14, 2020
Grant Date -
Jun 6, 2019
app pub date -
Oct 22, 2018
filing date -
Dec 5, 2017
priority date (Note) -
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Abstract
A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
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