Semiconductor memory devices and methods of operating semiconductor memory devices
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United States of America Patent
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Jul 7, 2020
Grant Date -
Nov 14, 2019
app pub date -
Dec 11, 2018
filing date -
May 10, 2018
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Abstract
A semiconductor memory device includes a memory cell array and an address decoder. The memory cell array includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of dynamic memory cells coupled to word-lines and bit-lines, each of the plurality of memory blocks are divided into a plurality of row blocks by row block identity bits of a row address, and each of the of row blocks includes a plurality of sub-array blocks arranged in a first direction. The address decoder changes a physical row address of a memory cell that stores or outputs data based on a column address received with a write command or a read command.
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