Semiconductor integrated circuit device including nano-wire selector and method of manufacturing the same
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United States of America Patent
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Jun 9, 2020
Grant Date -
Jan 31, 2019
app pub date -
Oct 2, 2018
filing date -
Aug 26, 2016
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Abstract
In a method of manufacturing a semiconductor integrated circuit device, an active region including a nano-wire may be formed on a bulk insulating layer. A hard mask pattern may be formed to partially expose the nano-wire. A work function-controlling region may be formed on the nano-wire exposed through the hard mask pattern. The hard mask pattern may be removed. A gate insulating layer may be formed on the nano-wire. A gate may be formed to surround the nano-wire.
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