Method of bias temperature instability calculation and prediction for MOSFET and FinFET

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United States of America Patent

PATENT NO 10621386
SERIAL NO

15464116

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Abstract

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A method, a system and a non-transitory machine-readable storage medium are provided. In one or more aspects, a computer-implemented method for bias temperature instability (BTI) calculation of a device includes simulating the device, using an electronic design automation tool. The simulation includes determining a first degradation value after applying a first sequence of stress values to the device for a first plurality of time steps. The simulation further includes determining a first degradation recovery value after the first plurality of time steps. The simulation further includes determining a first recovered degradation value after the first plurality of time steps by combining the first degradation value and the first degradation recovery value. The first degradation value, the first degradation recovery value, and the first recovered degradation value are associated with one or more model parameters of the device. The simulation is a transient analysis simulation, and the device is a FINFET or MOSFET device.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Alvin San Jose, US 44 148
Guo, Shaofeng Beijing, CN 3 0
Guo, Tianlei Beijing, CN 1 0
Huang, Chunyi Beijing, CN 3 4
Huang, Ru Beijing, CN 100 354
Li, Yanhui Beijing, CN 51 68
Liao, Si-Yu Beijing, CN 1 0
Wang, Runsheng Beijing, CN 20 98
Xie, Jushan San Jose, US 7 37
Yu, Zhuoqing Beijing, CN 1 0

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