Critical methodology in vacuum chambers to determine gap and leveling between wafer and hardware components

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 10599043
APP PUB NO 20180046088A1
SERIAL NO

15675101

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Abstract

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Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.

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Patent Owner(s)

Patent OwnerAddress
APPLIED MATERIALS INC3050 BOWERS AVENUE SANTA CLARA CA 95054

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gilbert, Rick San Jose, US 12 496
Khaja, Abdul Aziz San Jose, US 58 1148
Lee, Jeongmin Sunnyvale, US 57 229
Narasimha, Karthik Thimmavajjula San Francisco, US 9 83
Ogiso, Hiroyuki Sunnyvale, US 26 176
Park, Sang Heon Fremont, US 7 49
Prabhakar, Vinay Cupertino, US 20 139
Rocha-Alvarez, Juan Carlos San Carlos, US 226 10949
Su, Zonghui San Jose, US 4 293
Zhou, Jianhua Campbell, US 140 4007

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