Wafer level packaging method

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 10580823
APP PUB NO 20180323227A1
SERIAL NO

15586102

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Abstract

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A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

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Patent Owner(s)

Patent OwnerAddress
UNITED MICROELECTRONICS CORPHSIN-CHU CITY 300

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ding, Wen-Bo Singapore, SG 3 163
Hsu, Chien-En Singapore, SG 10 221
Pang, Chien-Kee Singapore, SG 11 165
Sheng, Zhi-Rui Singapore, SG 4 165
Zhang, Sheng Singapore, SG 265 1612

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