System and method for managing peak power demand and noise in non-volatile memory array
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United States of America
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Mar 3, 2020
Grant Date -
Sep 26, 2019
app pub date -
Jun 21, 2018
filing date -
Jun 21, 2018
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Abstract
A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.
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