Device having write assist circuit including memory-adapted transistors and method for making the same
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United States of America
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Feb 4, 2020
Grant Date -
Oct 18, 2018
app pub date -
Apr 10, 2018
filing date -
Apr 10, 2018
priority date (Note) -
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Abstract
A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.
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