Cache-coherent multiprocessor system and a method for detecting failures in a cache-coherent multiprocessor system

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United States of America

PATENT NO 10540284
APP PUB NO 20160034398A1
SERIAL NO

14445237

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Abstract

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A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

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Patent Owner(s)

Patent OwnerAddress
NXP USA INC6501 WILLIAM CANNON DRIVE AUSTIN TX 78735

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bibel, Oliver Grasbrunn, DE 5 38
Fader, Joachim Munich, DE 12 91
Von, Wendorff Wilhard Christophorus Munich, DE 11 60
Wendel, Dirk Grasbrunn, DE 23 100

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