Debugging translation block and debugging architecture
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United States of America Patent
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Nov 12, 2019
Grant Date -
Nov 15, 2018
app pub date -
May 10, 2017
filing date -
May 10, 2017
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Abstract
An electronic device includes one or more integrated circuits, a debugging translation block, and a bus connected to the one or more integrated circuits and the debugging translation block, the bus configured to provide a connection to one or more external devices, wherein the debugging translation block is configured to receive debugging commands from a testing host device via the bus, convert the debugging commands into debugging input data, and provide the debugging input data to a debugging state machine of a first integrated circuit of the one or more integrated circuits.
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