Semiconductor chip and multi-chip package using thereof and method for manufacturing the same
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United States of America Patent
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Oct 8, 2019
Grant Date -
Apr 26, 2018
app pub date -
Dec 21, 2017
filing date -
Jun 22, 2016
priority date (Note) -
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Abstract
The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.
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