FPGA/ASIC framework and method for requirements-based trust assessment
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United States of America
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Sep 10, 2019
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app pub date -
Mar 1, 2017
filing date -
Mar 1, 2017
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Abstract
Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.
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