Metrology target identification, design and verification

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United States of America Patent

PATENT NO 10387608
APP PUB NO 20180032662A1
SERIAL NO

15727477

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Abstract

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A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.

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Patent Owner(s)

Patent OwnerAddress
KLA-TENCOR CORPORATIONONE TECHNOLOGY DRIVE MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adel, Michael Ya'akov, IL 46 1696
Chang, Ellis Saratoga, US 32 1401
Dror, Chen Tivon, IL 4 30
Shusterman, Tal Haifa, IL 3 40

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