Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
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United States of America Patent
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Aug 20, 2019
Grant Date -
Jun 7, 2012
app pub date -
Sep 30, 2011
filing date -
Dec 31, 2007
priority date (Note) -
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Abstract
Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.
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