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United States of America Patent

PATENT NO 10374386
SERIAL NO

16003074

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Abstract

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A chip may include a first substantially planar isolation layer with a first surface and a second surface opposite the first surface. The chip may include a first substantially planar conduction layer with a first surface positioned adjacent to the second surface of the first isolation layer and a second surface opposite the first surface. The chip may include a second substantially planar isolation layer with a first surface positioned adjacent to the second surface of the first conduction layer and a second surface opposite the first surface. The chip may include a second conduction layer etched on the second surface of the second isolation layer. The second conduction layer may include an anode trace, a cathode trace, and an optical transmitter positioned on the cathode trace. The chip may include one or more vias through the second isolation layer electrically coupling the anode trace with the first conduction layer.

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Patent Owner(s)

Patent OwnerAddress
II-VI DELAWARE INC1110 NORTH MARKET STREET 4TH FLOOR WILMINGTON DE 19890

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amirkiai, Maziar Sunnyvale, US 26 178
Deng, Hongyu Saratoga, US 50 533
Ding, Frank Lei Milpitas, US 6 15
Mu, Jianwei Pleasanton, US 33 79
Wu, Tao Union City, US 372 4736

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