High voltage architecture for non-volatile memory
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United States of America Patent
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Aug 6, 2019
Grant Date -
Dec 21, 2017
app pub date -
Jun 27, 2017
filing date -
Jun 15, 2015
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Abstract
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).
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