Gate with self-aligned ledge for enhancement mode GaN transistors
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United States of America Patent
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Jun 4, 2019
Grant Date -
Nov 2, 2017
app pub date -
Jul 20, 2017
filing date -
Apr 8, 2009
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Abstract
An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.
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