Clock divider device and methods thereof
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United States of America Patent
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May 28, 2019
Grant Date -
Aug 30, 2018
app pub date -
Feb 24, 2017
filing date -
Feb 24, 2017
priority date (Note) -
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Abstract
A method for implementing clock dividers includes providing, in response to detecting a voltage drop at a processor core, an input clock signal to a transmission gate multiplexer for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit, and modifying the set of core clock enable signals to generate the stretch-enable signals. An output clock signal is generated based on the selected stretch-enable signal.
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