Reception interface circuits supporting multiple communication standards and memory systems including the same
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United States of America Patent
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May 14, 2019
Grant Date -
Oct 5, 2017
app pub date -
Jan 3, 2017
filing date -
Mar 31, 2016
priority date (Note) -
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Abstract
A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
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