Random time generated interrupts in a cryptographic hardware pipeline circuit
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United States of America Patent
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Apr 23, 2019
Grant Date -
Oct 25, 2018
app pub date -
Apr 25, 2017
filing date -
Apr 25, 2017
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Abstract
Apparatus and method for defending against a side-channel information attack such as a differential power analysis (DPA) attack. In some embodiments, a cryptographic hardware pipeline circuit performs a selected cryptographic function upon a selected set of data over a processing time interval. The pipeline circuit has a sequence of stages connected in series. The stages are enabled responsive to application of an asserted enable signal. An enable interrupt circuit is configured to periodically interrupt the selected cryptographic function to provide a plurality of processing intervals interspersed with the interrupt intervals. At least a selected one of the processing intervals or the interrupt intervals have random durations selected responsive to a series of random numbers.
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