Clock synchronizer and method of establishing an output clock
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United States of America Patent
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Apr 23, 2019
Grant Date -
Dec 28, 2017
app pub date -
Sep 7, 2017
filing date -
Apr 2, 2003
priority date (Note) -
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Abstract
A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.
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