Distortion reduction of memory openings in a multi-tier memory device through thermal cycle control
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United States of America Patent
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Mar 5, 2019
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N/A
app pub date -
Jun 27, 2017
filing date -
Jun 27, 2017
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Abstract
A first tier structure is provided by forming first memory openings through a first alternating stack of first insulating layers and first spacer layers, and by forming sacrificial memory opening fill structures in the first memory openings. A second tier structure is formed over the first tier structure by forming a second alternating stack of second insulating layers and second spacer layers. Second memory openings are formed through the second tier structure in areas of the sacrificial memory opening fill structures. Distortion of the first tier structure and misalignment between the first and second memory openings is reduced or prevented by conducting thermal cycles at a lower temperature for the second tier structure than for the first tier structure.
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