One-time programmable (OTP) memory device for reading multiple fuse bits
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United States of America Patent
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Feb 5, 2019
Grant Date -
Apr 19, 2018
app pub date -
Jul 24, 2017
filing date -
Oct 14, 2016
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Abstract
A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.
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