Systems, methods, and apparatus for memory cells with common source lines
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 29, 2019
Grant Date -
Mar 22, 2018
app pub date -
Oct 12, 2017
filing date -
Dec 2, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully