Reduction of defects in wafer level chip scale package (WLCSP) devices
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United States of America Patent
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Jan 8, 2019
Grant Date -
Jun 22, 2017
app pub date -
Mar 6, 2017
filing date -
Mar 21, 2015
priority date (Note) -
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Abstract
Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
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