Clock control trees
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United States of America Patent
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Dec 4, 2018
Grant Date -
N/A
app pub date -
Nov 27, 2017
filing date -
Nov 27, 2017
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Abstract
A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.
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