Edge trim processes and resultant structures
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United States of America Patent
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Nov 20, 2018
Grant Date -
Nov 24, 2016
app pub date -
May 21, 2015
filing date -
May 21, 2015
priority date (Note) -
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Abstract
Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.
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