Low leakage ReRAM FPGA configuration cell
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United States of America Patent
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Nov 13, 2018
Grant Date -
Mar 22, 2018
app pub date -
Nov 27, 2017
filing date -
Dec 17, 2015
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Abstract
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.
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