Memory control circuit
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United States of America Patent
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Oct 23, 2018
Grant Date -
Oct 2, 2014
app pub date -
Apr 1, 2014
filing date -
Apr 2, 2013
priority date (Note) -
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Abstract
The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.
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