Process for filling vias in the microelectronics
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United States of America Patent
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Oct 16, 2018
Grant Date -
Sep 1, 2016
app pub date -
May 6, 2016
filing date -
Jan 26, 2011
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Abstract
A process for metalizing a through silicon via feature in a semiconductor integrated circuit device, the process including, during the filling cycle, reversing the polarity of circuit for an interval to generate an anodic potential at said metalizing substrate and desorb leveler from the copper surface within the via, followed by resuming copper deposition by re-establishing the surface of the copper within the via as the cathode in the circuit, thereby yielding a copper filled via feature.
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