Method and apparatus for coupling up a voltage-setting transistor for a control line in a programming operation

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United States of America Patent

PATENT NO 10037810
SERIAL NO

15634006

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Abstract

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The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES INC951 SANDISK DRIVE LEGAL DEP MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amarnath, Anirudh San Jose, US 14 75
Cernea, Raul-Adrian Santa Clara, US 131 7455
Shukla, Hemant Edinburgh, GB 7 25
Singh, Saurabh Kumar Edinburgh, GB 18 66
Yadala, Sridhar Bangalore, IN 26 271

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