Method and apparatus for manufacturing three-dimensional-structure memory device

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United States of America Patent

PATENT NO 10006121
SERIAL NO

14189391

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Abstract

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Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.

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Patent Owner(s)

Patent OwnerAddress
EUGENE TECHNOLOGY CO LTD42 CHUGYE-RO YANGJI-MYEON CHEOIN-GU YONGIN-SI GYEONGGI-DO 17156

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cho, Sung Kil Gyeonggi-do, KR 9 112
Jang, Gil Sun Chungcheongnam-do, KR 7 132
Kim, Hai Won Gyeonggi-do, KR 26 705
Oh, Wan Suk Gyeonggi-do, KR 8 110
Shin, Seung Woo Gyeonggi-do, KR 69 3024
Woo, Sang Ho Gyeonggi-do, KR 33 1093

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