YANFEI ZHANG
Inventor
Stats
- 2 US patents issued
- 22 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 2 US Patents Issued
- 22 US Applications Filed
- 9 Total Citation Count
- Aug 9, 2023 Most Recent Filing
- Sep 18, 2018 Earliest Filing
Work History
No Work History Available.Inventor Addresses
Address | Duration |
---|---|
Beijing, CN | Feb 25, 20 - Dec 22, 20 |
Beijing, IN | Sep 12, 19 - Sep 12, 19 |
Hangzhou, CN | Oct 07, 21 - May 14, 24 |
Shandong, CN | Oct 11, 22 - Oct 11, 22 |
Shanghai, CN | Mar 05, 20 - Sep 19, 23 |
Shenzhen, CN | Oct 22, 24 - Oct 22, 24 |
Wuxi, CN | Jan 06, 22 - Feb 18, 25 |
Zibo City, CN | Nov 02, 23 - Nov 02, 23 |
Zibo, CN | Dec 03, 20 - Aug 06, 24 |
Technology Profile
Technology | Matters | |
---|---|---|
A01C: | PLANTING; SOWING; FERTILISING | 1 |
A01H: | NEW PLANTS OR PROCESSES FOR OBTAINING THEM; PLANT REPRODUCTION BY TISSUE CULTURE TECHNIQUES | 1 |
A61K: | PREPARATIONS FOR MEDICAL, DENTAL, OR TOILET PURPOSES | 1 |
Patents / Publication
Patents / Publication # | Year of Publication / Issued | Title | Citations |
---|---|---|---|
12229029 | 2025 | Apparatus and method for testing high-speed low-latency interconnect interface (HLII) for silicon interposer | 0 |
D1048255 | 2024 | Splash toy | 3 |
D1048213 | 2024 | Splash toy | 0 |
12119069 | 2024 | Anti-fuse memory reading circuit with controllable reading time | 0 |
12099377 | 2024 | Clock skew-adjustable chip clock architecture of programmable logic chip | 0 |
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level.
>
Upgrade to our Level for up to -1 portfolios!.