John J Zasio
Inventor
Stats
- 18 US patents issued
- 18 US Applications filed
- most recent filing
This is official USPTO record data
Details
- 18 US Patents Issued
- 18 US Applications Filed
- 698 Total Citation Count
- Aug 25, 1995 Most Recent Filing
- Oct 31, 1977 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| FUJITSU MICROELECTRONICS LIMITED | 1
| 1990
|
| TERADYNE, INC. | 2
| 1988
|
| STORAGE TECHNOLOGY PARTNERS (THROUGH STC COMPUTER RESEARCH CORPORATION, MANAGING GENERAL PARTNER), | 1
1 | 1982
1983 |
| Amdahl Corporation | 1
| 1977
|
| AIDA Corporation | 1
| 1986
|
| DUET TECHNOLOGIES, INC. | 2
| 1988
|
| FUJITSU LIMITED | 1
1 1 1 1 2 | 1977
1978 1979 1982 1987 1995 |
| Storage Technology Partners | 1
1 2 2 | 1981
1982 1983 1984 |
Inventor Addresses
| Address | Duration |
|---|---|
| Sunnyvale, CA | Mar 04, 80 - Oct 29, 96 |
Technology Profile
| Technology | Matters | |
|---|---|---|
| A61K: | PREPARATIONS FOR MEDICAL, DENTAL, OR TOILET PURPOSES | 1 |
| B01J: | CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS, COLLOID CHEMISTRY; THEIR RELEVANT APPARATUS | 1 |
| B23K: | SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 5570036 | 1996 | CMOS buffer circuit having power-down feature | 1 |
| 5541528 | 1996 | CMOS buffer circuit having increased speed | 7 |
| 5095356 | 1992 | Cellular integrated circuit and hierarchical method | 15 |
| 4969029 | 1990 | Cellular integrated circuit and hierarchial method | 13 |
| 4937770 | 1990 | Simulation system | 41 |
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